Semiconductor integrated circuit

ABSTRACT

A first counter detects a rising edge of a clock signal, and generates a first signal having a multiplied cycle of the clock signal. A second counter detects a falling edge of the clock signal, and generates a second signal having a multiplied cycle of the clock signal. A first line transfers the first signal, while a second line transfers the second signal. A phase comparator is connected to the first line and the second line to generate a third signal based on a phase difference between the first signal and the second signal and output the third signal to one of the circuit units. A plurality of the phase comparators are connected to the first line and the second line, and are disposed between one of the ends of the first line and the second line and one of the circuit units.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Division of co-pending U.S. patent applicationSer. No. 12/533,573, filed on Jul. 31, 2009, the entire contents ofwhich are incorporated herein by reference.

This application is based on and claims the benefit of priority fromprior Japanese Patent Application No. 2008-199131, filed on, Aug. 1,2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit, andmore particularly, to a semiconductor integrated circuit having a clocksignal generation circuit.

2. Description of the Related Art

In a semiconductor integrated circuit, dispersion in delay time of theclock signal may occur among plurality of wiring lines, because ofchanges in phase, duty cycle or the like of the clock signal. This mightcause an error in functions of various circuits. Therefore, in a knownmethod (JP H11-194848A), buffers are arranged on the clock signal linesin a tree-like form (referred to as a clock tree hereinbelow) toequalize delay time of the clock signal at circuits to which the clocksignal is supplied.

However, when a clock tree with the large number of hierarchy is formed,a logic delay occurs to a cell positioned at the terminal of the clocktree, and access time deteriorates. In addition, since the clock treestructure may increase the area of the semiconductor integrated circuitbecause it needs buffers therein. Since the conventional art has theabove-mentioned problem, it is difficult to provide a smallsemiconductor integrated circuit with a tolerance against changes inphase, duty cycle or the like of the clock signal.

SUMMARY OF THE INVENTION

The semiconductor integrated circuit according to one aspect of thepresent invention comprises: a plurality of circuit units arrangedtherein; a first counter configured to detect a rising edge of a clocksignal and generate a first signal having a multiplied cycle of theclock signal; a second counter configured to detect a falling edge ofthe clock signal and generate a second signal having a multiplied cycleof the clock signal; a first line for transferring the first signal; asecond line for transferring the second signal; and a phase comparatorconnected to the first line and the second line to generate a thirdsignal based on a phase difference between the first signal and thesecond signal and output the third signal to one of the circuit units,the phase comparator being disposed on the first line and the secondline, and plurality of the phase comparators being disposed between endsof the first line and the second line and the circuit units.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a structure of the semiconductor integrated circuit100 according to an embodiment of the present invention.

FIG. 2 is a graph showing states of the clock signal CLK in each partwhen the clock signal CLK is transferred in the semiconductor integratedcircuit 100.

FIG. 3 illustrates another structure of the circuit unit 10.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Next, a semiconductor integrated circuit according to the presentembodiment of the present invention is described with reference todrawings.

[Structure of Semiconductor Integrated Circuit of Embodiment]

FIG. 1 schematically illustrates the semiconductor integrated circuit100 according to the embodiment. As shown in FIG. 1, the semiconductorintegrated circuit 100 according to the present embodiment mainlycomprises a plurality of circuit units 10, a first counter 11, a secondcounter 12, inverters INV, buffers BUF, and phase comparators 13.

The circuit units 10 each may be a microcomputer, a memory or the like.Plural circuit units 10 are disposed in the semiconductor integratedcircuit 100. In FIG. 1, four circuit units 10 are arranged in thesemiconductor integrated circuit 100, but the present invention is notlimited to the specific number.

The first counter 11 has a clock terminal 11A, data input terminal 11B,and a data output terminal 11C. The first counter 11 receives a clocksignal CLK as an input at the clock terminal 11A. When the first counter11 detects a rising edge of the clock signal CLK, it outputs a firstsignal PUL1 from the data output terminal 11C. The first signal PUL1 hasa multiplied cycle (ex. double) of the clock signal CLK.

The second counter 12 has a clock terminal 12A, a data input terminal12B, and a data output terminal 12C. The second counter 12 receives aclock signal CLK as an input at the clock terminal 12A. When the secondcounter 11 detects a falling edge of the clock signal CLK, it outputs asecond signal PUL2 from the data output terminal 12C. The second signalPUL2 has a multiplied cycle (ex. double) of the clock signal CLK.

The output terminal 11C of the first counter 11 is connected to theinput terminal 12B of the second counter 12. Moreover, the outputterminal 12C of the second counter 12 is connected to the input terminal11A of the first counter 11 via the inverter INV1.

The phase comparator 13 has a first data input terminal 13A, a seconddata input terminal 13B, and a data output terminal 13C. The data inputterminal 13A is connected to the output terminal 11C of the firstcounter 11, while the data input terminal 13B is connected to the outputterminal 12C of the second counter 12. Contrary to the above-describedconnection, it is also possible that the data input terminal 13A isconnected to the output terminal 12C, and the data input terminal 13B isconnected to the output terminal 11C. Note that in the example explainedbelow, the data input terminal 13A is connected to the output terminal11C of the first counter 11, and the data input terminal 13B isconnected to the output terminal 12C of the second counter 12.

The first output terminal 11C of the first counter and the data inputterminal 13A of the phase comparator 13 are connected via a first line80. The second output terminal 12C of the second counter 12 and the datainput terminal 13B of the phase comparator 13 are connected via a secondline 90. Therefore, a first signal PUL1 is transferred through the firstline 80, while the second signal PUL2 is transferred through the secondline 90.

Depending on the situation, the first line 80 and the second line 90 maybe provided with a buffer BUF arranged thereon. In this embodiment, abuffer BUF1 is disposed on the first line 80, and a buffer BUF2 isdisposed on the second line 90. The number of the buffers BUF, however,is not limited to the specific number shown in FIG. 1.

The phase comparator 13 receives the first signal PUL1 and the secondsignal PUL2, and generates a third signal PUL3 based on a phasedifference between the first signal PUL1 and the second signal PUL2. Thethird signal PUL3 is output from the output terminal 13C.

The plural phase comparators 13 are provided for respective circuitunits 10, and disposed between ends of the first line 80 and second line90 and the circuit units 10. Therefore, the first line 80 branches offinto plural branches from the first counter 11. Each of the pluralbranches is connected to a data input terminal 13A of the phasecomparator 13. Similarly, the second line 90 branches off into pluralbranches from the second counter 12. Each of the plural branches isconnected to a data input terminal 13B of the phase comparator 13. Notethat, in FIG. 1, the number of the phase comparators 13 is four, thenumber being in accordance with that of the circuit units 10 in FIG. 1.However, the invention is not limited to the number or the relationshipshown in FIG. 1.

The phase comparator 13 is formed of an EX-OR gate (an Exclusive ORgate). Alternatively, it may includes inverters INV provided at theinput terminals of the EX-NOR gate. In this embodiment, the phasecomparator 13 includes a first inverter INV2 (a first inverter), asecond inverter INV3 (a second inverter) and an EX-NOR gate 14 (referredto as a comparator 14 hereinbelow). Therefore, the input terminals 13A,13B of the phase comparator 13 are connected to the input terminals ofinverters INV2, INV3, respectively. Moreover, the output terminal 13C ofthe phase comparator 13 is connected to an output terminal of thecomparator 14.

The inverter INV2 receives the first signal PUL1 and outputs an invertedsignal REV1 (a first inverted signal) of the first signal PUL1 to thecomparator 14.

The inverter INV3 receives the second signal PUL2 and outputs aninverted signal REV2 (a second inverted signal) of the second signalPUL2 to the comparator 14.

The comparator 14 receives the inverted signals REV1 and REV2, andgenerates, based on these signals, a third signal PUL3 indicating aphase difference between the inverted signal REV1 and the invertedsignal REV2. The third signal PUL2 is output to the circuit unit 10.

As described above, the phase comparator 13 is disposed between the endsof the first line 80 and the second line 90 and the circuit units 10.Therefore, the first line 80 and the second line 90 are designed so thatthey have a larger wiring lengths than wiring lines disposed between thephase comparators 13 and the circuit units 10, and wiring lines fortransferring the clock signal CLK to be supplied to the first counter 11and the second counter 12. One of the feature of the present embodimentresides in this.

The reason why the first line 80 and second line have such large wiringlengths is described hereinbelow. The clock signal CLK swings at ahigher frequency (double, for example) than other signals (addresssignals, data signals, or the like, not illustrated). Therefore, it ismore likely to suffer, compared to the other signals, a signaldistortion thereof due to the wiring line resistance of the transmissionline or the stray capacitance thereof (hereinafter referred to as awiring time constant). Therefore, when the wiring time constant is toolarge, the clock signal CLK does not swing enough, and the device endsup in operation failure.

Therefore, it is necessary for the lines for transferring the clocksignal CLK, the first signal PUL1, the second signal PUL2, the firstinverted signal REV1, the second inverted signal REV2 and the thirdsignal PUL3 to be formed to have a smaller wiring time constant than thelines for transferring other signals such as address signals or datasignals. For example, each of the lines for transferring theabove-mentioned signals is formed to have a wiring time constant that isless than the half cycle of these signals.

However, as described above, the semiconductor integrated circuit 100according to the present embodiment is configured so that the firstcounter 11 and the second counter 12 convert the clock signal CLK intothe first signal PUL1 and the second signal PUL2 having a multipliedcycle of the clock signal CLK. Since the first signal PUL1 and thesecond signal PUL2 have a smaller frequency than the clock signal CLK,waveform distortion due to the wiring time constant is relatively small,and it does not greatly affect the operation of the clock signal CLK. Asdescribed above, it is possible to employ a design where the first lineand the second line for transferring the first signal PUL1 and thesecond signal PUL2 have large wiring lengths.

However, it is not appropriate that the inverter INV2 and the inverterINV3 formed on the first line 80 and the second line 90 are located atthe respective positions where the wiring time constant thereof aredifferent from each other. This is because this may vary the phases ofthe inverted signals REV1 and REV2 generated at the inverters 2 and 3.When the phases of the inverted signals REV1 and REV2 vary, it may varythe duty cycle of the third signal PUL3 generated based on the phasedifference between the inverted signals REV1 and REV2. Then, the thirdsignal PUL3 having a duty cycle different from that of the clock signalCLK is transferred to each of the circuit units 10. This leads to anoperation error in the circuit units 1. Therefore, the inverter INV2 andthe inverter INV3 are disposed at the respective positions where wiringtime constants of the first line 80 and the second line 90 are equal.

Note that resistors and capacitors illustrated on the first line 80 andthe second line 90 do not mean devices actually disposed thereon as realelements, but means wiring resistances and stray capacitances includedin the first line 80 and second line 90.

With the structure of this embodiment, signals may be transferred toeach circuit without varying a clock frequency or a duty cycle thereofdue to a wiring time constant of the transfer line, even if a high clockfrequency and a high duty ratio is used. Moreover, the number of buffersdisposed on the clock transfer lines may be smaller. This may reduce thearea of the semiconductor integrated circuit 100.

[Operation of Semiconductor Integrated Circuit 100 According to FirstEmbodiment]

Next, an operation of the semiconductor integrated circuit 100 accordingto the first embodiment is described with reference to FIG. 2. FIG. 2 isa timing chart illustrating the states of the signals in each part whenthe clock signal CLK is transferred to the circuit units 10.

The clock signal CLK is transferred to a first clock terminal 11A of thecounter 11 and to the clock terminal 12A of the second counter 12. Thefirst counter 11 generates the first signal PUL1 from the rising edge ofthe clock signal CLK, and the first signal PUL1 is output into the firstline 80 from the data output terminal 11C. The second counter 12generates the second signal PUL2 from the falling edge of the clocksignal CLK, and the second signal PUL2 is output into the second line 90from the data output terminal 12C.

The first signal PUL1 and the second signal PUL2 are generated to have amultiplied cycle of the clock signal CLK (a doubled cycle, for example).Therefore, as shown in FIG. 2, one cycle of the first signal PUL1 andthe second signal PUL2 are generated for two cycles of the clock signalCLK.

In the semiconductor integrated circuit 100 according to thisembodiment, the first line 80 and the second line 90 may have largerwiring lengths compared to the other lines. Therefore, a wiring timeconstant thereof becomes higher. Accordingly, the first signal PUL1 andthe second signal PUL2 transmitting in the first line 80 and the secondline 90 has distorted waveforms due to the wiring time constant as shownin FIG. 2.

The inverter INV2 generates the first inverted signal REV1 by invertingthe first signal PUL1, and outputs the first inverted signal REV1 to thecomparator 14. The inverter INV3 generates the second inverted signalREV2 by inverting the second signal PUL2, and outputs the secondinverted signal REV2 to the comparator 14.

The comparator 14 generates the third signal PUL3 from a phasedifference of the first inverted signal REV1 and the second invertedsignal REV2, and output it to the circuit unit 10.

The inverter INV2 and the inverter INV3 are disposed at the respectivepositions where wiring time constants of the first line 80 and thesecond line 90 are equal. Therefore, the threshold voltage of theinverter INV2 and the inverter INV3 are set equal. This enables thephase difference between the first inverted signal REV1 and secondinverted signal REV2 to be substantially equal to that between the firstsignal PUL1 and the second signal PUL2. Then, the third signal PUL3having substantially the same frequency and substantially the same dutycycle as the clock signal CLK is transferred from the comparator 14 tothe circuit unit 10.

Having explained the embodiment of the present invention, the presentinvention is not limited to the specific embodiment. Various changes,addition, substitution is possible in the present embodiment withoutdeparting the spirit or the scope of the invention. For example, in theembodiment described above, the clock signal CLK is transferred to thecircuit units 10 such as a microcomputer or a memory. The Clock signalCLK may be transferred to a memory cell array, as shown in FIG. 3. Anysemiconductor integrated circuits in which a clock signal CLK istransferred are included in the scope of the present invention,regardless of the size of the semiconductor integrated circuit 100.

Moreover, in the above-described embodiment, the first counter 11 andthe second counter 12 is formed with a flip-flop. They may be formed ofa combination of logic gates, as far as the same operation may beperformed.

1. A semiconductor integrated circuit, comprising: a plurality ofcircuit units arranged therein; a first counter configured to detect arising edge of a clock signal and generate a first signal having amultiplied cycle of the clock signal; a second counter configured todetect a falling edge of the clock signal and generate a second signalhaving a multiplied cycle of the clock signal; a first line fortransferring the first signal; a second line for transferring the secondsignal; and a phase comparator connected to the first line and thesecond line to generate a third signal based on a phase differencebetween the first signal and the second signal and output the thirdsignal to one of the circuit units, the phase comparator being disposedon the first line and the second line, and plurality of the phasecomparators being disposed between ends of the first line and the secondline and the circuit units.
 2. The semiconductor integrated circuitaccording to claim 1, wherein the phase comparator comprises: a firstinverter connected to the first line and configured to generate a firstinverted signal as a inverted signal of the first signal; a secondinverter connected to the second line and configured to generate asecond inverted signal as a reversed signal of the second signal; and acomparator connected to the first inverter and the second inverter togenerate the third signal based on a phase difference between the firstinverted signal and the second inverted signal.
 3. The semiconductorintegrated circuit according to claim 2, wherein the first inverter andthe second inverter are disposed at positions so that the wiring timeconstant of the first line and the wiring time constant of the secondline are equal.
 4. The semiconductor integrated circuit according toclaim 1, wherein a buffer is provided on the first line and the secondline.
 5. The semiconductor integrated circuit according to claim 1,wherein the first line and the second line are disposed with a pluralityof branches, and the ends of the plurality of branches are connected tothe phase comparators, respectively.
 6. The semiconductor integratedcircuit according to claim 5, wherein the phase comparator comprises: afirst inverter connected to the first line and configured to generate afirst inverted signal as a inverted signal of the first signal; a secondinverter connected to the second line and configured to generate asecond inverted signal as a inverted signal of the second signal; and acomparator connected to the first inverter and the second inverter togenerate the third signal based on a phase difference between the firstinverted signal and the second inverted signal.
 7. The semiconductorintegrated circuit according to claim 5, wherein the first inverter andthe second inverter are disposed at positions so that the wiring timeconstant of the first line and the wiring time constant of the secondline are equal.
 8. The semiconductor integrated circuit according toclaim 5, wherein the wiring time constant of the first line and thewiring time constant of the second line are less than half of the cyclesof the first signal and the second signal transferred on the first lineand the second line.
 9. The semiconductor integrated circuit accordingto claim 5, wherein a buffer is provided on the first line and thesecond line.